This disclosure relates generally to the field of semiconductor manufacturing, and in particular, to test structures for diagnosing contact shorts in a static random access memory (SRAM) device.
In the manufacture of semiconductors, processing induced defects, which result in physical defects within the semiconductor product, continue to be a problem. Exemplary of processing induced defects that cause circuit failure are open circuits in conductive lines and short circuits between adjacent conductive lines.
With the improvements in lithographic imaging processes, a semiconductor wafer may be provided with increasingly fine features that allow for smaller device dimensions and higher density devices. However, these features are often smaller than the wavelength of light used to transfer the pattern onto the wafer. As features become increasingly smaller, it has become increasingly more difficult to accurately transfer the pattern onto the wafer.
Conventional approaches aimed at solving the above problem include the use of phase-shifted masks and assist features on the mask. Phase-shifted masks selectively alter the phase of the light transmitted through the mask in order to improve the resolution of the features on the wafer. Assist features, by contrast, are used to pattern isolated high aspect features by nesting these otherwise isolated features in order to take advantage of photoresist and tools which are optimized to pattern nested features.
Another approach for minimizing process-induced defects has been through the use of fabricating test structures during the integrated circuit manufacturing process. These test structures serve to collect data on the health of the semiconductor structure. The principal reason for this is that the integrated circuits themselves cannot be probed because the interconnections in the device are neither accessible electrically, nor can the regions be isolated from one another to provide accurate data. The typical monolithic integrated semiconductor circuit involves such a dense pattern of impurity regions and metallurgy interconnecting them that the components cannot be readily isolated for testing purposes. Thus, semiconductor designers have found it necessary to design test structures where different components of the semiconductor process can be individually evaluated.
One manufacturing approach is the fabrication of defect monitors on the same wafers on which the actual semiconductor devices are fabricated. In this manner, the defect monitors are fabricated under the same processing environment and at the same time as the actual semiconductor devices, such that these defect monitors more accurately replicate the processing induced defects in the actual products.
These defect monitors are typically fabricated within the kerf or discardable portion of the semiconductor wafer, and may include a metal serpentine line, one or more interdigitated metal lines, and/or one or more metal combs. As for the serpentine metal line, electrical continuity is checked whereby if a current cannot flow through the serpentine line, then an indication is made that the serpentine line is broken. Electrical continuity is also checked between the interdigitated metal lines and/or one or more metal combs, whereby if a current can flow between such lines or combs, then this implies that there is bridging (or shorting) across the gap where there should not be any conductors.
The simplistic design of most electrical defect process monitors, however, samples only a fraction of the design space and process development, and often does not provide an exact location of where the actual defects reside within the semiconductor wafer. In particular, current electrical defect monitors may be able to test for and locate defects in the contact array region of the device; however, they do not precisely pinpoint exactly where these electrical defects reside within such region. That is, typical defect test monitors are limited to locating an electrical defect within the contact array region, whereby the located defect may reside between two adjacent contacts, between two adjacent metal lines residing above the contacts, or even between two adjacent polysilicon lines residing below the contacts. As such, once an electrical defect is located within this region of the wafer, it is often necessary to use non-electrical methods, such as physical examination, for locating exactly where the electrical defect resides in the wafer. Not only are these conventional electrical defect detection methods extremely time consuming, but they also do not isolate contact-to-contact shorts from the variety of other types of electrical defects residing within this region of the wafer.
Thus, while current test structures may be useful for limited purposes, there is still a need in the art for improved and more reliable test structures that will enhance the efficiency of the semiconductor manufacturing process, and in particular, will quickly and easily isolate contact-to-contact shorts from various other electrical defects within a wafer.
Additionally, as transistor size scales down, it becomes more challenging to fill the canyon that is located between the gate structures on a semiconductor wafer with the contact dielectric layers. The process window for contact dielectric formation is relatively small, and variations in shallow trench isolation (STI) recess depth, gate length, spacer shape and contact dielectric conformality may result in the presence of voids in the contact dielectric. An example of such a void is shown in FIG. 1, which shows a cross section of a portion of a SRAM semiconductor device 100 including a void 107. Semiconductor device 100 includes a p-type substrate 101, with STI regions 102 formed in the substrate 101. Source/drain regions, including n-type source/drain implanted regions 103 located in p-type wells 110, p-type source/drain regions 104 located in the n-type wells 111, and gate stacks 106 are formed on the p-type substrate 101. Contacts 105 contact the source/drain regions 103/104. The device 100 is covered in contact dielectric layers, including nitride layer 108 and oxide layer 109. Void 107 occurs during formation of the nitride contact dielectric layer 108, and runs parallel to gate stacks 106. Void formation may also occur in oxide layer if the nitride layer is relatively thin. A void such as void 107 may be filled with a conductive material such as aluminum (Al), titanium nitride (TiN) and/or tungsten (W) during subsequent metallization of the semiconductor device; this kind of defect (referred to as a subway) can cause contact-to-contact (CA-CA) shorts and yield degradation. It is important to detect subway defects as early in the process sequence as possible.
Test structures including a comb structure have been developed to detect subways at the first metal level (M1). However, the turnaround time may be relatively long for such test structures and the signal can be clouded by variations introduced by the M1 module (like M1-M1 shorts). A test structure that includes a comb structure is not capable of distinguishing between direct CA-CA shorts due to the presence of a subway and indirect CA-CA shorts that are formed by contact-to-gate line (CA-PC) shorts. A detected short may be located anywhere within the comb structure, so failure analysis requires additional steps to pinpoint the location of a detected short. Comb test structures also lack the ability to monitor for the presence of subways in a semiconductor device that comprises a static random access memory (SRAM), which may be more prone to subway formation due to relatively tight device density.
Direct inspection of SRAM using e-beam inspection (EBI) has also been developed to detect subways before the first metal level (M1). By observing grounded contacts under EBI, the presence of some subways in SRAM may be determined. However, EBI may only detect a subset of subways, and some of the undetected subways could be more susceptible, thus causing device failure. Secondly, EBI is not able to differentiate a direct subway fail versus other potential failure mechanisms, such as indirect shorts between contacts through adjacent gate lines.
A typical SRAM cell layout is shown in FIG. 2A. Region 201 covers one bit of a SRAM device 200A, including p-type source/drain implant regions 202 and n-type source-drain implant region 203. Region 204 represents a diffusion area on which transistors are formed with the p-type source/drain implanted regions 202. Region 205 represents a gate area that forms the controlling gate of the transistor in region 204. Three different types of contacts are present in the SRAM device 200B. Regular contact (CA) 206, connecting to a diffusion area 204, may be bright under EBI depending on the ground conditions. Rectangular contact (CArec) 207 provides connection between diffusion, gate and metal level. Regular contact 208, connecting to a gate line, is isolated from the diffusion area and thus always ungrounded in EBI.
An example of a SRAM device 200B including subways is shown in FIG. 2B. SRAM device 200B includes a p-type source/drain implant region 211 that is located on an n-type well (such as n-type well 111 of FIG. 1) and n-type source/drain implant region 212 that is located on the p-type well (such as p-type well 110 of FIG. 1). The p-type source/drain implant regions 211 include both CAs 213 and rectangular CAs (CArecs) 214. CArecs 214 are contacts that bridge both a source/drain and a gate line, such as gate line 215. For bulk semiconductors under positive mode EBI conditions, the CAs in p-type region 211 will appear bright because the p-type region 211 will be forward biased to the n-well that is located under the p-type region 211 which serves as a virtual ground. N-type source/drain implant region 212 includes CAs 216 (which may be node or bit line or ground CAs), and word line CAs 217. CAs in n-type region 212 will typically appear dark during EBI because the junction between the n-type region 212 and the p-well located under the n-type region 212 will be reverse biased. Shorts in the SRAM device 200B include direct CA-CA subway shorts 218, 219, and 220, and indirect CA-CA short (i.e., CA-PC short) 221. Subway 219 will cause CA 216 to appear bright under EBI. However, because the gate lines in p-type source/drain implant region 211, such as gate line 215, are grounded to a p-type source/drain by a CArec 214, an indirect CA-CA short 221 though the gate line 215 will cause CA 216 to become grounded and appear bright under EBI. Therefore, the indirect CA-CA short 221 will be indistinguishable from the subway short 219. Subways 218 and 220 cannot be detected by EBI because either end of subway 218, and either end of subway 220, is at the same potential during EBI.